A PLL based 1. 2 GHz LO generator with digital phase control in 9. CMOSA 1. 2 GHz PLL with digital output phase control has been implemented in a 9. CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 1. GHz, with a common 1. GHz reference. The chip, including pads, measures 1. Each PLL consumes 1. Car Test 2000 there. A from a 1. 2 V supply, with a typical measured phase noise of 1. Program Za Kalkulacije Cijena. BcHz at 1 MHz offset. The phase control range exceeds 3. Complementary metaloxidesemiconductor, abbreviated as CMOS s i m s, is a technology for constructing integrated circuits. CMOS technology is used in. Vol. 7, No. 3, May, 2004. Mathematical and Natural Sciences. Study on Bilinear Scheme and Application to Threedimensional Convective Equation Itaru Hataue and Yosuke.